Connect Tech JB1 Specifications

NNeexxyyss33™™ BBooaarrdd RReeffeerreennccee MMaannuuaall Revision: April 3, 2013 1300 Henley Court | Pullman, WA 99163 (509) 334 6306 Voice and

Nexys3 Reference Manual Doc: 502-182 page 10 of 22 Shared signalsADDR(25:0)DATA(15:0)P30-RST Cellular RAMRAM onlyMT-CREMT-LBMT-UBMT-CEWEOEParalle

Nexys3 Reference Manual Doc: 502-182 page 11 of 22 Ethernet PHY The Nexys3 board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8710)

Nexys3 Reference Manual Doc: 502-182 page 12 of 22 Spartan 6L12PIC24FJ192K_CLKJ13“HOST”J42L13K14K_DATM_CLKM_DATR13R15DINCLKFPGA Serial programmin

Nexys3 Reference Manual Doc: 502-182 page 13 of 22 incorrect bit files will automatically be rejected. Note the PIC24 reads the FPGA's mode,

Nexys3 Reference Manual Doc: 502-182 page 14 of 22 FE Resend. FE directs keyboard to re-send most recent scan code. FF Reset. Resets the keyboa

Nexys3 Reference Manual Doc: 502-182 page 15 of 22 VGA Port The Nexys3 board uses 10 FPGA signals to create a VGA port with 8-bit color and

Nexys3 Reference Manual Doc: 502-182 page 16 of 22 those rays are fed by the current that flows into the cathodes. These particle rays are initia

Nexys3 Reference Manual Doc: 502-182 page 17 of 22 corresponds to the number of horizontal passes the cathode makes over the display area, and a

Nexys3 Reference Manual Doc: 502-182 page 18 of 22 Basic I/O The Nexys3 board includes eight slide switches, five push buttons, eight individual

Nexys3 Reference Manual Doc: 502-182 page 19 of 22 Seven-Segment Display The Nexys3 board contains a four-digit common anode seven-segment LED d

Nexys3 Reference Manual Doc: 502-182 page 2 of 22 Configuration After power-on, the Spartan-6 FPGA board must be configured (or programmed) befo

Nexys3 Reference Manual Doc: 502-182 page 20 of 22 asserted, then a “7” will be displayed in digit position 2. If AN0 and CB, CC are driven for 4

Nexys3 Reference Manual Doc: 502-182 page 21 of 22 Spartan 68PmodA888PmodBPmodCPmodDBank2Bank3Bank3Bank0* VHDC Connector Pinout IO1-P: B2 IO1-N:

Nexys3 Reference Manual Doc: 502-182 page 22 of 22 Built-In Self Test A demonstration configuration is loaded into the BPI PCM device on the Nex

Nexys3 Reference Manual Doc: 502-182 page 3 of 22 JTAG (both jumpers loaded), and board power is cycled. The FPGA will automatically reject any .

Nexys3 Reference Manual Doc: 502-182 page 4 of 22 Adept System Digilent's Adept high-speed USB2 system can be used to program the FPGA and

Nexys3 Reference Manual Doc: 502-182 page 5 of 22 The configuration tool supports programming from any valid ROM file produced by the Xilinx tool

Nexys3 Reference Manual Doc: 502-182 page 6 of 22 Register I/O The register I/O tab requires that a corresponding IP block, available in the Pa

Nexys3 Reference Manual Doc: 502-182 page 7 of 22 I/O Expand The I/O Expand tab works with an IP block in the FPGA to provide additional simpl

Nexys3 Reference Manual Doc: 502-182 page 8 of 22 Power JackBatteryConnectorPower SelectJumper JP1VU1.8V2.5V1.2V3.3VIC13: LTC3633ENPowerSwitchP

Nexys3 Reference Manual Doc: 502-182 page 9 of 22 controller (similar to any SRAM controller). When operated in synchronous mode, continuous tran